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Qualcomm announces first ever mass-market RISC-V Android SoC
However, the Android ecosystem for RISC-V has to start somewhere, and that start has been made.

The Android ecosystem is rapidly moving toward a RISC-V future. Last year, Google announced official RISC-V support in Android and plans to make it a “tier one platform” on par with Arm. Now that support in the OS is in place, hardware is needed, and Qualcomm is announcing the first ever mass-market RISC-V Android SoC.
The processor doesn’t have a name yet, but Qualcomm says it’s developing the “RISC-V Snapdragon Wear” chip in collaboration with Google. The company says it plans to “commercialize the RISC-V-based wearable device solution globally, including in the United States.” For Google and Qualcomm, the chip represents the first commercial attempt to use RISC-V with Android, and as far as we can tell, it’s the first announced RISC-V chip for the mass market. Qualcomm claims that the groundwork it and Google have laid “will help pave the way for new products in the Android ecosystem that can take advantage of low-power, high-performance custom processors.”
RISC-V is a big threat to the Arm processor architecture that currently dominates all mobile devices. The RISC-V architecture is open source, which could make it cheaper and more flexible than Arm. If companies want to develop their own chips, they can do so without paying license fees to Arm.
RISC-V is also a way to get around all sorts of problems associated with Arm. Arm is the backbone of many large tech companies, but the company has fallen on hard times over the past few years as its parent company Softbank looks to get rid of its investment. Softbank originally wanted to sell Arm to Nvidia. After regulators blocked that deal, Arm decided to go for an IPO. In an effort to impress shareholders, Arm has changed its business model in an attempt to charge significantly more than before. Arm is also currently suing Qualcomm, one of its largest partners, over license fees related to its acquisition of chip developer Nuvia. In addition, Arm has become a major weapon in the trade war between the US and China, causing Chinese companies to rally around RISC-V as an international alternative. The U.S. government is concerned that RISC-V is a way to circumvent U.S. influence over chip export controls.
This is not the first time Qualcomm has shipped a RISC-V core, and the company recently announced a joint venture to promote RISC-V. RISC-V is now used in several chips as secondary microcontrollers that are part of larger SoC Arm. All of them are still considered Arm chips, as all the major processor cores are still owned by Arm. RISC-V has quickly gained traction in the microcontroller world because it only has to work within a specific chip and doesn’t have the issues with the broader software ecosystem that full-system CPUs have to deal with. The Snapdragon 865 in 2019 was Qualcomm’s first chip to use RISC-V for some microcontrollers, and to date, Qualcomm says “more than 650 million RISC-V cores have been shipped.” However, none of these have been mainstream system processors.
For RISC-V as a system processor to become a viable platform for Android, a lot of work needs to be done. Developer SDKs, compilers, libraries, and a million other things need to support the new architecture. Google is working on a huge to-do list to bring Android to a viable level with RISC-V. The good news is that since typical Android apps are written in Java (or Kotlin) and compiled for the device using the Android Runtime (ART) program, all Google has to do to support the apps is get ART to generate RISC-V code, and most of the apps will work. The exception is code written using the Android NDK, which allows you to create high-performance native C and C++ code. Many games (not relevant to wearable devices) and libraries use it.
However, the Android ecosystem for RISC-V has to start somewhere, and that start has been made. Qualcomm states that “a timeline for launching a commercial RISC-V-based product for wearable devices will be disclosed at a later date.”
